HIGH SPEED VIDEO RECORDING SYSTEM ON A CHIP FOR DETONATION JET ENGINE TESTING Full article
| Source | MATEC Web of Conferences Compilation, EDP Sciences. 2018. |
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| Output data | Year: 2018, Volume: 158, Article number : 01028, Pages count : 5 DOI: 10.1051/matecconf/201815801028 | ||
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Abstract:
This article describes system on a chip development for high speed video recording purposes. Current research was started due to
difficulties in selection of FPGAs and CPUs which include wide bandwidth, high speed and high number of multipliers for real time signal
analysis implementation. Current trend of high density silicon device integration will result soon in a hybrid sensor-controller-memory circuit
packed in a single chip. This research was the first step in a series of experiments in manufacturing of hybrid devices. The current task is high
level syntheses of high speed logic and CPU core in an FPGA. The work resulted in FPGA-based prototype implementation and examination.
Cite:
Samsonov A.N.
, Samoilova K.V.
HIGH SPEED VIDEO RECORDING SYSTEM ON A CHIP FOR DETONATION JET ENGINE TESTING
In compilation MATEC Web of Conferences. – EDP Sciences., 2018. – Т.158. DOI: 10.1051/matecconf/201815801028 Scopus РИНЦ OpenAlex
HIGH SPEED VIDEO RECORDING SYSTEM ON A CHIP FOR DETONATION JET ENGINE TESTING
In compilation MATEC Web of Conferences. – EDP Sciences., 2018. – Т.158. DOI: 10.1051/matecconf/201815801028 Scopus РИНЦ OpenAlex
Identifiers:
| Scopus: | 2-s2.0-85047770136 |
| Elibrary: | 35524499 |
| OpenAlex: | W2792680737 |